1. Field of the Invention
The present invention relates to a wiring technology for a semiconductor apparatus and particularly relates to a wiring technology for a solid-state image pickup apparatus.
2. Description of the Related Art
A semiconductor apparatus has an input pad to which a signal is input from an external part of a semiconductor chip and an output pad for outputting a signal to the external part.
Japanese Patent Laid-Open No. 2008-78354 discloses pads in a semiconductor apparatus and a wiring layout. The semiconductor apparatus described in FIG. 1 of Japanese Patent Laid-Open No. 2008-78354 has power supply wirings (4a and 4b) for an internal circuit arranged so as to completely surround a periphery of the internal circuit. Then, first power supply pads (8a and 8b) for the internal circuit are formed while being integrated with the power supply wiring for the internal circuit. Furthermore, second power supply pads (7a and 7b) for the internal circuit are arranged in an outer area of a chip.
In the above-described layout, the wirings intersect mutually. To be more specific, a power supply wiring for supplying a power supply voltage to the internal circuit from the second power supply pads intersects the power supply wiring for the internal circuit. For that reason, according to Japanese Patent Laid-Open No. 2008-78354, the layout is disclosed in which the wiring for supplying the power supply to the internal circuit from the second power supply pads is overlapped in a planar view with the first power supply pads.
In general, with regard to the semiconductor apparatus, the number of semiconductor chips that can be obtained from one sheet of wafer (chip yield) is set to be large. For this reason, it is demanded that devices that realize the same function and purpose are arranged in a semiconductor chip of a smallest possible area.